***************************************************************************** * 68HC11 INTERNAL REGISTERS * * * * This header contains EQUates for all the internally addressable registers * * and bits for the 68HC11A8 * ***************************************************************************** * * BIT IS CLEARED ON RESET * BIT IS SET ON RESET * BIT IS UNDEFINED ON RESET * TIME WRITE ONCE BIT CAN ONLY BE CHANGED ONCE WITHIN THE * FIRST 64 BUS CYCLES AFTER RESET * <1> DIRECT CLEARING FLAG * FLAG IS CLEARED BY WRITING 1 INTO IT (STRANGE BUT TRUE) *---------------------------------------------------------------------------- REGBAS EQU $1000 ; BASE ADDRESS PRESUMING INIT REGISTER = $1x PORTA EQU $0000 ; PORT A DATA REGISTER BIT7 EQU %10000000 BIT6 EQU %01000000 BIT5 EQU %00100000 BIT4 EQU %00010000 BIT3 EQU %00001000 BIT2 EQU %00000100 BIT1 EQU %00000010 BIT0 EQU %00000001 PIOC EQU $0002 ; PARALLEL I/O CONTROL REGISTER STAF EQU %10000000 ; STROBE A FLAG STAI EQU %01000000 ; STROBE A INTERRUPT ENABLE CWOM EQU %00100000 ; PORT C WIRE-OR MODE HNDS EQU %00010000 ; HANDSHAKE/SIMPLE STROBE MODE SELECT OIN EQU %00001000 ; OUTPUT/INPUT HANDSHAKE SELECT PLS EQU %00000100 ; PULSE MODE SELECT FOR STRB OUTPUT EGA EQU %00000010 ; ACTIVE EDGE SELECT FOR STRA INVB EQU %00000001 ; INVERT STRB OUTPUT PORTC EQU $0003 ; PORT C DATA REGISTER PORTB EQU $0004 ; PORTB DATA REGISTER PORTCL EQU $0005 ; PORT C LATCHED DATA REGISTER DDRC EQU $0007 ; DATA DIRECTION REGISTER FOR PORT C PORTD EQU $0008 ; PORT D DATA REGISTER DDRD EQU $0009 ; DATA DIRECTION REGISTER FOR PORT D PORTE EQU $000A ; PORT E DATA REGISTER CFORC EQU $000B ; TIMER COMPARE FORCE REGISTER FOC1 EQU %10000000 ; <1> FOC2 EQU %01000000 ; <1> FOC3 EQU %00100000 ; <1> FOC4 EQU %00010000 ; <1> FOC5 EQU %00001000 ; <1> *0 ; *0 ; *0 ; OC1M EQU $000C ; OUTPUT COMPARE 1 MASK REGISTER OC1M7 EQU %10000000 ; OC1M6 EQU %01000000 ; OC1M5 EQU %00100000 ; OC1M4 EQU %00010000 ; OC1M3 EQU %00001000 ; *0 ; *0 ; *0 ; OC1D EQU $000D ; OUTPUT COMPARE 1 DATA REGISTER OC1D7 EQU %10000000 ; OC1D6 EQU %01000000 ; OC1D5 EQU %00100000 ; OC1D4 EQU %00010000 ; OC1D3 EQU %00001000 ; *0 ; *0 ; *0 ; TCNT EQU $000E ; TIMER COUNTER REGISTER (2 BYTES) TIC1 EQU $0010 ; TIMER INPUT CAPTURE REGISTER_1 (2 BYTES) TIC2 EQU $0012 ; TIMER INPUT CAPTURE REGISTER_2 (2 BYTES) TIC3 EQU $0014 ; TIMER INPUT CAPTURE REGISTER_3 (2 BYTES) TOC1 EQU $0016 ; TIMER OUTPUT COMPARE REGISTER_1 (2 BYTES) TOC2 EQU $0018 ; TIMER OUTPUT COMPARE REGISTER_2 (2 BYTES) TOC3 EQU $001A ; TIMER OUTPUT COMPARE REGISTER_3 (2 BYTES) TOC4 EQU $001C ; TIMER OUTPUT COMPARE REGISTER_4 (2 BYTES) TOC5 EQU $001E ; TIMER OUTPUT COMPARE REGISTER_5 (2 BYTES) TCTL1 EQU $0020 ; TIMER CONTROL REGISTER_1 OM2 EQU %10000000 ; OL2 EQU %01000000 ; OM3 EQU %00100000 ; OL3 EQU %00010000 ; OM4 EQU %00001000 ; OL4 EQU %00000100 ; OM5 EQU %00000010 ; OL5 EQU %00000001 ; TCTL2 EQU $0021 ; TIMER CONTROL REGISTER_2 *0 ; *0 ; EDG1B EQU %00100000 ; EDG1A EQU %00010000 ; EDG2B EQU %00001000 ; EDG2A EQU %00000100 ; EDG3B EQU %00000010 ; EDG3A EQU %00000001 ; TMSK1 EQU $0022 ; TIMER INTERRUPT MASK REGISTER_1 OC1I EQU %10000000 ; OC2I EQU %01000000 ; OC3I EQU %00100000 ; OC4I EQU %00010000 ; OC5I EQU %00001000 ; IC1I EQU %00000100 ; IC2I EQU %00000010 ; IC3I EQU %00000001 ; TFLG1 EQU $0023 ; TIMER INTERRUPT FLAG REGISTER_1 OC1F EQU %10000000 ; <1> OC2F EQU %01000000 ; <1> OC3F EQU %00100000 ; <1> OC4F EQU %00010000 ; <1> OC5F EQU %00001000 ; <1> IC1F EQU %00000100 ; <1> IC2F EQU %00000010 ; <1> IC3F EQU %00000001 ; <1> TMSK2 EQU $0024 ; TIMER INTERRUPT MASK REG_2 TOI EQU %10000000 ; TIMER OVERFLOW INTERRUPT ENABLE RTII EQU %01000000 ; RTI INTERRUPT ENABLE PAOVI EQU %00100000 ; PULSE ACCUMULATOR OVERFLOW INTERRUPT ENABLE PAII EQU %00010000 ; PULSE ACCUMULATOR INPUT INTERRUPT ENABLE *0 ; *0 ; PR1 EQU %00000010 ; PR0 EQU %00000001 ; TFLG2 EQU $0025 ; TIMER INTERRUPT FLAG REG_2 TOF EQU %10000000 ; TIMER OVERFLOW FLAG <1> RTIF EQU %01000000 ; REAL TIME (PERIODIC) INTERRUPT FLAG <1> PAOVF EQU %00100000 ; PULSE ACCUMULATOR OVERFLOW FLAG <1> PAIF EQU %00010000 ; PULSE ACCUMULATOR INPUT EDGE FLAG <1> *0 *0 *0 *0 PACTL EQU $0026 ; PULSE ACCUMULATOR CONTROL REGISTER DDRA7 EQU %10000000 ; DATA DIRECTION FOR PA7 PAEN EQU %01000000 ; PULSE ACCUMULATOR SYSTEM ENABLE PAMOD EQU %00100000 ; PULSE ACCUMULATOR MODE PEDGE EQU %00010000 ; PULSE ACCUMULATOR EDGE CONTROL *0 *0 RTR1 EQU %00000010 ; RTR0 EQU %00000001 ; PACNT EQU $0027 ; PULSE ACCUMULATOR COUNT REGISTER SPCR EQU $0028 ; SPI CONTROL REGISTER SPIE EQU %10000000 ; SPI INTERRUPT ENABLE SPE EQU %01000000 ; SPI SYSTEM ENABLE DWOM EQU %00100000 ; PORT D WIRE-OR MODE MSTR EQU %00010000 ; MASTER/SLAVE MODE SELECT CPOL EQU %00001000 ; CLOCK POLARITY CPHA EQU %00000100 ; CLOCK PHASE SPR1 EQU %00000010 ; SPI CLOCK (SCK) RATE BIT SPR0 EQU %00000001 ; SPI CLOCK (SCK) RATE BIT SPSR EQU $0029 ; SPI STATUS REGISTER SPIF EQU %10000000 ; SPI INTERRUPT REQUEST WCOL EQU %01000000 ; WRITE COLLISION STATUS FLAG *0 ; MODF EQU %00010000 ; SPI MODE ERROR INTERRUPT STATUS FLAG *0 *0 *0 *0 SPDR EQU $002A ; SPI DATA REGISTER BAUD EQU $002B ; SCI BAUD RATE CONTROL REGISTER TCLR EQU %10000000 ; CLEAR BAUD COUNTER CHAIN (TEST ONLY) *0 SCP1 EQU %00100000 ; SERIAL PRESCALER SELECTS SCP0 EQU %00010000 ; SERIAL PRESCALER SELECTS RCKB EQU %00001000 ; SCI BAUD RATE CLOCK TEST (TEST ONLY) SCR2 EQU %00000100 ; SCI RATE SELECT BIT 2 SCR1 EQU %00000010 ; SCI RATE SELECT BIT 1 SCR0 EQU %00000001 ; SCI RATE SELECT BIT 0 SCCR1 EQU $002C ; SCI CONTROL REGISTER 1 R8 EQU %10000000 ; RECEIVE BIT 8 T8 EQU %01000000 ; TRANSMIT BIT 8 *0 M EQU %00010000 ; MODE SELECT WAKE EQU %00001000 ; WAKE = WAKE UP (BY ADDRESS MARK/IDLE) *0 *0 *0 SCCR2 EQU $002D ; SCI CONTROL REGISTER 2 TIE EQU %10000000 ; TRANSMIT INTERRUPT ENABLE TCIE EQU %01000000 ; TRANSMIT COMPLETE INTERRUPT ENABLE RIE EQU %00100000 ; RECEIVER INTERRUPT ENABLE ILIE EQU %00010000 ; IDLE LINE INTERRUPT ENABLE TE EQU %00001000 ; TRANSM. EN.(TOGGLE TO QUEUE IDLE CHAR) RE EQU %00000100 ; RECEIVER ENABLE RWU EQU %00000010 ; RECEIVER WAKE-UP CONTROL SBK EQU %00000001 ; SEND BREAK SCSR EQU $002E ; SCI STATUS REGISTER TDRE EQU %10000000 ; TRANSMIT DATA REG EMPTY FLAG TC EQU %01000000 ; TRANSMIT COMPLETE FLAG RDRF EQU %00100000 ; RECEIVE DATA REG FULL FLAG IDLE EQU %00010000 ; IDLE LINE DETECTED FLAG OR EQU %00001000 ; OVER-RUN ERROR FLAG NF EQU %00000100 ; NOISE ERROR FLAG FE EQU %00000010 ; FRAMING ERROR FLAG *0 SCDR EQU $002F ; SCI DATA REGISTER ADCTL EQU $0030 ; A/D CONTROL/STATUS REGISTER CCF EQU %10000000 ; CONVERSIONS COMPLETE FLAG *0 SCAN EQU %00100000 ; CONTINUOUS SCAN CONTROL MULT EQU %00010000 ; MULT.CHANNEL/SINGLE CHANNEL CONTROL CD EQU %00001000 ; CC EQU %00000100 ; CB EQU %00000010 ; CA EQU %00000001 ; ADR1 EQU $0031 ; ADR2 EQU $0032 ; ADR3 EQU $0033 ; ADR4 EQU $0034 ; RESVD2 EQU $0035 ; UNUSED RESVD3 EQU $0036 ; UNUSED RESVD4 EQU $0037 ; UNUSED RESVD5 EQU $0038 ; UNUSED OPTION EQU $0039 ; SYSTEM CONFIGURATION OPTIONS ADPU EQU %10000000 ; A TO D POWER UP CSEL EQU %01000000 ; CLK SELECT.SHOULD BE USED IF E < 1MHZ IRQE EQU %00100000 ; IRQ SEL. EDGE SENS. ONLY(TIME PROTECTED) DLY EQU %00010000 ; EN.OSC.START UP DEL.(EXITING FROM STOP) CME EQU %00001000 ; CLOCK MONITOR ENABLE *0 CR1 EQU %00000010 ; COP TIMER RATE SELECT BIT_1 CR0 EQU %00000001 ; COP TIMER RATE SELECT BIT_0 COPRST EQU $003A ; ARM/RESET COP TIMER CIRCUITRY PPROG EQU $003B ; EEPROM PROGRAMMING REGISTER ODD EQU %10000000 ; PROGRAM ODD ROWS IN HALF OF EEPROM (TEST) EVEN EQU %01000000 ; PROGRAM EVEN ROWS IN HALF OF EEPROM (TEST) *0 BYTE EQU %00010000 ; BYTE/OTHER EEPROM ERASE MODE ROW EQU %00001000 ; ROW/ALL EEPROM ERASE MODE ERASE EQU %00000100 ; ERASE/NORMAL CONTROL OF EEPROM EELAT EQU %00000010 ; EEPROM LATCH CONTROL EEPGM EQU %00000001 ; EEPROM PROGRAM CMD.; WRITABLE ONLY IF EELAT = 1 HPRIO EQU $003C ; HIGHEST PRIORITY INTERRUPT AND MISC. RBOOT EQU %10000000 ; READ BOOTSTRAP ROM (ONLY WRITABLE IF SMOD=1) SMOD EQU %01000000 ; MODE SELECT MDA EQU %00100000 ; MODE SELECT IRV EQU %00010000 ; INTERNAL READ VISIBILITY PSEL3 EQU %00001000 ; \ PSEL2 EQU %00000100 ; \ PRIORITY SELECT PSEL1 EQU %00000010 ; / MAY ONLY BE WRITTEN IF I BIT IN CC REG IS 1 PSEL0 EQU %00000001 ; / INIT EQU $003D ; RAM AND I/O MAPPING REGISTER RAM3 EQU %10000000 ; RAM2 EQU %01000000 ; RAM1 EQU %00100000 ; RAM0 EQU %00010000 ; REG3 EQU %00001000 ; REG2 EQU %00000100 ; REG1 EQU %00000010 ; REG0 EQU %00000001 ; TEST1 EQU $003E ; FACTORY TEST REGISTER TILOP EQU %10000000 ; TEST ILLEGAL OPCODE *0 OCCR EQU %00100000 ; OUTPUT CONDITION CODE REG STAT TO TIMER PORT CBYP EQU %00010000 ; TIMER DIVIDER CHAIN BYPASS DISR EQU %00001000 ; DISABLE RESETS FROM COP AND CLOCK MONITOR FCM EQU %00000100 ; FORCE CLOCK MONITOR FAILURE FCOP EQU %00000010 ; FORCE COP WATCHDOG FAILURE TCON EQU %00000001 ; TEST CONFIGURATION CONFIG EQU $003F ; CONFIGURATION CONTROL REGISTER *0 *0 *0 *0 NOSEC EQU %00001000 ; SECURITY MODE DISABLE (MASK) NOCOP EQU %00000100 ; COP SYSTEM DISABLE ROMON EQU %00000010 ; ROM ENABLE EEON EQU %00000001 ; EEPROM ENABLE * ---------------------------------------------------------- * INTERRUPT VECTOR ASSIGNMENT * ---------------------------------------------------------- * $FFC0 - $FFD5 RESERVED * ---------------------------------------------------------- VECSCI EQU $FFD6 ; SCI SERIAL SYSTEM VECSPI EQU $FFD8 ; SPI SERIAL TRANSFER COMPLETE VECPAI EQU $FFDA ; PULSE ACC INPUT EDGE VECPAO EQU $FFDC ; PULSE ACC OVERFLOW VECTOV EQU $FFDE ; TIMER OVERFLOW VECTO5 EQU $FFE0 ; TIMER OUTPUT COMPARE 5 VECTO4 EQU $FFE2 ; TIMER OUTPUT COMPARE 4 VECTO3 EQU $FFE4 ; TIMER OUTPUT COMPARE 3 VECTO2 EQU $FFE6 ; TIMER OUTPUT COMPARE 2 VECTO1 EQU $FFE8 ; TIMER OUTPUT COMPARE 1 VECTI3 EQU $FFEA ; TIMER INPUT CAPTURE 3 VECTI2 EQU $FFEC ; TIMER INPUT CAPTURE 2 VECTI1 EQU $FFEE ; TIMER INPUT CAPTURE 1 VECRTI EQU $FFF0 ; REAL TIME INTERRUPT VECIRQ EQU $FFF2 ; IRQ VECXIRQ EQU $FFF4 ; XIRQ VECSWI EQU $FFF6 ; SWI VECILL EQU $FFF8 ; ILLEGAL OPCODE TRAP VECCOP EQU $FFFA ; COP FAILURE (RESET) VECCMF EQU $FFFC ; COP CLOCK MONITOR FAIL (RESET) VECRES EQU $FFFE ; RESET *-----------------------------------------------------------